1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device for a stack package and a read data skew control method thereof.
2. Discussion of Related Art
A package consisting of at least two semiconductor memory devices, that is, at least two semiconductor memory chips, is called a stack package. FIG. 1 is a schematic showing of a stack package. As shown in FIG, 1, a top memory chip 11 is disposed above a bottom memory chip 13. An output pad PAD of the top memory chip 11 is connected to a ball 15 by means of a bonding wire 14. Another output pad PAD of the bottom memory chip 13 is connected to a ball 17 by means of a bonding wire 18, and the bail 15 is connected to the ball 17 by means of a bonding wire 19.
When the ball 17 is used for data output, for example, read data from the bottom memory chip 13 is output through the relatively short bonding wire 18, and read data from the top memory chip 11 is output through a relatively longer bonding wire, that is, the bonding wire 14 plus the bonding wire 19. Accordingly, the load of the bonding wire 19 is added to the output pad of the top memory chip 11, which is not the case for the output pad of the bottom memory chip 13. Therefore, read data from the top memory chip 11 is output hundreds of pico-seconds slower than read data from the bottom memory chip 13.
As a result, the overall read time, that is, from the point of time when an external clock signal is applied to a memory chip to the point of time when the read data is output, of the top memory chip 11 is longer than the overall read time of the bottom memory chip 33. This reduces a valid section of the data read from the top memory chip 11, as well as a time margin for data fetch in a memory controller that receives the read data.
To compensate the read data skew, that is, the time skew between the read data from the top memory chip 13 and the read data from, the bottom memory chip 13, a fuse for compensating for the read data skew can be included in a semiconductor memory chip. The points of time when data is output from the top memory chip or the bottom memory chip can be controlled by distinguishing the top memory chip and the bottom memory chip in fusing steps using the fuse. Alternatively, the points of time when data is output can be controlled after packaging using an electrical fuse (E-Fuse).
The use of a fuse is limited, however, in that fusing should be performed prior to packaging after the top memory chip and the bottom memory chip are distinguished as such in advance, and the use of an E-Fuse has problems in terms of reliability.